Physical networking equipment for providing multiple, virtual network devices is well known. Virtual devices, such as virtual servers, virtual switches, and virtual routers, help to provide support for different protocols and operating systems with a smaller physical footprint, among other things. The virtual device is typically implemented in software, and different instances of virtual devices may run in the same physical device by the same physical processor chip.
A current trend in processor architecture is to enhance performance by increasing the number of execution cores on a processor chip. Increasing the number of execution cores provides at least the possibility of increasing aggregate performance without reducing cycle time. However, increasing the number of CPU cores has the effect of increasing the complexity of the task of scheduling execution of threads of control. In particular, even if each thread of control operates at a lower frequency, the number of thread scheduling events for a given work load may increase because the number of threads of control increases. This problem is evident, for example, with Network Attached Storage (NAS) equipment because contention on the run queue lock results in lock data being accessed by different cores. Coherent access to memory which may be shared across multiple cores can be costly since each core must establish unique ownership of the specific cache line while performing a read/modify/write operations on a lock. Establishing unique ownership involves checking if the specific cache line is present in any of the other cores and requesting that it be written back to memory if it has been modified. Contention is also problematic because it is desirable for locks to be granted without contention for efficient fine-grained locking, but as the number of CPU cores increases, the probability of contention increases. The result can be negation of potential performance improvement from the multi-core CPU.